1. Field of the Invention
The invention generally relates to semiconductor testing and, more particularly, to testing dynamic random access memory (DRAM) devices.
2. Description of the Related Art
The evolution of sub-micron CMOS technology has resulted in an increasing demand for high-speed semiconductor memory devices, such as dynamic random access memory (DRAM) devices, pseudo static random access memory (PSRAM) devices, and the like. Herein, such memory devices are collectively referred to as DRAM devices.
During the manufacturing process, multiple DRAM devices are typically fabricated on a single silicon wafer and undergo some form of testing (commonly referred to as wafer or “front-end” test) before the devices are separated and packaged individually. Such testing typically entails writing test data patterns to a particular series of address locations, reading data back from the same address locations, and comparing the data patterns read back to the data patterns written, in order to verify device operation. In conventional wafer testing, to avoid contention on data buses shared between multiple banks of DRAM memory cells, a single bank is accessed at a time. In a standard test mode, all lines of a shared bus may be used. During a single bank read access, a burst of data is read from the bank, for example, with multiple bits of data read at each clock edge.
In some cases, in an effort to reduce the amount of test data that must be passed between devices and a tester, the data read from the device arrays may be compressed. For example, for some DRAM architectures, 16 bits of data may be read in each access to the array at every clock edge. These 16 bits may be compressed internally to 4 bits, for example, by comparing four data bits stored at cells formed at an intersection of a word line (WL) and a column select line (CSL), with a test data pattern written to those bits, to generate a single “pass/fail” bit. Because repair algorithms typically replace entire wordlines and/or column select lines (depending on the particular repair algorithm) that have a failing cell with redundant wordlines and/or redundant column select lines, it is not necessary to know which particular cell or cells failed.
While such compression reduces the amount of test data that must be handled, having to access a single bank at a time limits the throughput of front-end testing. Accordingly, what is needed is a mechanism for improving throughput of front-end testing.